Semiconductor storage device and method of manufacturing the same

ABSTRACT

In a memory cell area (A) of a semiconductor storage device, a capacitor ( 8 ) formed on a first insulating layer ( 5 ) formed so as to cover MOS transistors ( 3, 4 ) includes a pillar-shaped insulating member ( 8   a ), a first capacitance electrode ( 8   b ) formed on the side surface of the pillar-shaped insulating member ( 8   a ), a capacitance insulating film ( 8   c ) formed on the first capacitance electrode ( 8   b ) and a second capacitance electrode ( 8   d ) formed on the capacitance insulating film ( 8   c ). A conductive member ( 7 ) for connecting the source or drain ( 3   a ) of the MOS transistor ( 3 ) to the first capacitance electrode ( 8   b ) is filled in a connection opening ( 6 ) formed in the first insulating layer ( 5 ). In a peripheral circuit area (B) other than the memory cell area (A) containing plural memory cells each having the MOS transistor ( 3 ) and the capacitor ( 8 ), a second insulating layer ( 9 ) which is formed simultaneously with the formation of the pillar-shaped insulating member ( 8   a ) of the capacitor ( 8 ) and has the same height as the pillar-shaped insulating member ( 8   a ) is formed on the first insulating layer ( 5 ).

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention belongs to the technical field of asemiconductor device, and particularly relates to a semiconductorstorage device having a memory cell area containing a capacitor and atransistor, and a method of manufacturing the semiconductor storagedevice.

[0003] 2. Description of the Related Art

[0004] In order to implement high storage capacity, a so-called stackstructure in which the electrode of a capacitor constituting a memorycell is three-dimensionally formed and it is disposed while superposedon a transistor has been applied to DRAM as a representative ofsemiconductor storage devices.

[0005]FIG. 9 is a schematic cross-sectional view showing theconventional DRAM thus constructed.

[0006] In FIG. 9, reference symbol A represents a memory cell area andreference symbol B represents a peripheral circuit area. Referencenumeral 10 represents a semiconductor substrate, reference numeral 12represents an element separation oxide film, reference numeral 14represents a MOS transistor for a memory cell constituting the memorycell area A, and reference numeral 16 represents a MOS transistorconstituting the peripheral circuit area B. Further, reference numeral14 a represents the source/drain of the MOS transistor 14, and referencenumeral 14 b represents the gate of the MOS transistor 14. Referencenumeral 16 a represents the source/drain of the MOS transistor 16, andreference numeral 16 b represents the gate of the MOS transistor 16.Reference numeral 18 represents an insulating layer, and referencenumeral 20 represents a connection opening formed in the insulatinglayer 18 and a conductive member 22 is filled in the connection opening20.

[0007] A cylindrical capacitance stack electrode 24 is formed at theposition corresponding to the conductive member 22 on the insulatinglayer 18, a capacitance insulating film 26 is formed on the side surfaceand top surface of the capacitance stack electrode 24, and a capacitanceplate electrode 28 is formed on the capacitance insulting film 26. Thesemembers construct a capacitor 30.

[0008] An insulating film (interlayer insulating film) 32 is formed onthe insulating layer 18 so as to cover the capacitor 30. Since desiredwires are formed on the insulating film 32, the upper surface of theinsulating film 32 is flattened to prevent the wires from being brokenduring the wire forming process.

[0009] The process of manufacturing DRAM as described above will bedescribed with reference to FIGS. 10 to 15.

[0010] First, as shown in FIG. 10, the element separation oxide film 12is formed on the semiconductor substrate 10, and the MOS transistors 14,16 and the insulating layer 18 is formed.

[0011] Subsequently, as shown in FIG. 11, the connection opening 20 isformed in the insulting layer 18, and the conductive member 22 is filledinto the connection opening 20.

[0012] Subsequently, as shown in FIG. 12, the capacitance stackelectrode 24 is formed at the position corresponding to the conductivemember 22, the capacitance insulating film 26 is formed on thecapacitance stack electrode 24, and a capacitance plate electrode 28 isformed on the capacitance insulating film 26, thereby forming thecapacitor 30.

[0013] Subsequently, the interlayer insulating film 32 is formed on theinsulating layer 18 as shown in FIG. 13. At this time, the upper surfaceof the interlayer insulating film 32 in the memory cell area A is higherthan the upper surface of the interlayer insulating film 32 in theperipheral circuit area B by the amount corresponding to the height ofthe capacitor 30. Therefore, the interlayer insulating film 32 of thememory cell area A is subjected to an etching treatment so that theupper surface of the interlayer insulting film 32 in the memory cellarea A is located at substantially the same height as the upper surfaceof the interlayer insulating film 32 in the peripheral circuit area B.In order to perform the etching treatment, a photoresist mask 34 isformed on the interlayer insulating film 32 in the peripheral circuitarea B.

[0014] Subsequently, as shown in FIG. 14, the etching treatment isconducted on the interlayer insulating film 32 of the memory cell area Ato substantially equalize the height of the interlayer insulating film32 in the memory cell area A with the height of the interlayerinsulating film 32 of the peripheral circuit area B.

[0015] Subsequently, as shown in FIG. 15, the photoresist mask 34 isremoved, and if necessary, an insulating film is further deposited tothereby form the interlayer insulating film 32 having the flat upperface (surface), thereby forming DRAM as shown in FIG. 9.

[0016] The above DRAM is described in NIKKEI MICRODEVICES, November(1993), p.31.

[0017] As described above, in the conventional DRAM, the capacitancestack electrode of the capacitor constituting the memory cell is formedof a pillar-shaped conductor, and thus there occurs a large differencein height (step) between the memory cell area and the peripheral circuitarea when the interlayer insulating film is formed. As a result, sinceit is necessary to secure the flatness of the surface of the interlayerinsulating film (particularly between the memory cell area and theperipheral circuit area) in order to smoothly form wires on theinterlayer insulating film in the subsequent step, a photolithographystep is further needed to selectively remove the interlayer insulatingfilm only in the memory cell area after the interlayer insulating filmis deposited as described above, and thus the number of steps isincreased.

SUMMARY OF THE INVENTION

[0018] Therefore, the present invention has been implemented to solvethe foregoing problems of the prior art, and has an object to provide asemiconductor device in which an insulating film such as an interlayerinsulating film having a flat surface can be formed without any specificstep of flattening the insulating film after the insulating film isdeposited, that is, without increasing the number of steps, and a methodof manufacturing the semiconductor device.

[0019] In order to attain the above object, according to a first aspectof the present invention, a semiconductor storage device having pluralmemory cells each containing a capacitor and a transistor ischaracterized in that a first insulating layer is formed so as to coverthe transistor, the capacitor is formed on the first insulating layer,the capacitor contains a pillar-shaped insulating member formed on thefirst insulating layer, a first capacitance electrode formed on the sidesurface of the pillar-shaped insulating member, a capacitance insulatingfilm formed on the first capacitance electrode and a second capacitanceelectrode formed on the capacitance insulating film, the firstinsulating layer has a connection opening formed therein, and theconnection opening is filled with a conductive member for connecting thefirst capacitance electrode and the transistor to each other.

[0020] In the semiconductor storage device described above, a secondinsulating layer formed of the same insulating material as thepillar-shaped insulating member of the capacitor is preferably formed atthe same height as the pillar-shaped insulating member of the capacitoron the first insulating layer in at least a part of an area other thanthe memory cell area containing the plural memory cells.

[0021] In the semiconductor storage device described above, thetransistor is preferably a MOS transistor, and the source or drain ofthe MOS transistor is connected to the conductive member.

[0022] According to a second aspect of the present invention, a methodof manufacturing a semiconductor storage device having plural memorycells each containing a capacitor and a transistor is characterized bycomprising the steps of: forming the transistor on a semiconductorsubstrate; forming a first insulating layer so that the transistor iscovered by the first insulating layer; forming connection openings inthe first insulating layer at the positions corresponding to therespective memory cells; filling a conductive member in each of theconnection openings; forming an insulating material layer on the firstinsulating layer; subjecting the insulating material layer to apatterning treatment to form a pillar-shaped insulating member so that apart of the surface of the conductive member filled in each of theconnection openings is covered by the pillar-shaped insulating member;forming a first capacitance electrode on the side surface of thepillar-shaped insulating member, connecting the first capacitanceelectrode and the conductive member to each other, forming a capacitanceinsulating film on the first capacitance electrode, and forming a secondcapacitance electrode on the capacitance insulating film.

[0023] In the semiconductor storage device manufacturing methoddescribed above, the patterning treatment of the insulating materiallayer is preferably performed by using anisotropic etching.

[0024] In the above semiconductor storage device manufacturing method,the formation of the first capacitance electrode is preferably performedby forming a conductive material layer and patterning the conductivematerial layer with anisotropic etching.

[0025] In the above semiconductor storage device manufacturing method,the transistor is preferably a MOS transistor, and each connectionopening is formed at the position corresponding to the source or drainof the MOS transistor.

[0026] In the above semiconductor storage device manufacturing method,it is preferable that the insulating material layer is also formed in anarea other than the memory cell area containing the plural memory cellson the semiconductor substrate, and the insulating material layer issubjected to a patterning treatment so that a second insulating layerhaving the same height as the pillar-shaped insulating member of thecapacitor remains in the area other than the memory cell area.

[0027] According to the present invention, the capacitor of the memorycell area is constructed while containing the pillar-shaped insulatingmember, and the pillar-shaped insulating member is formed simultaneouslywith formation of the interlayer insulating film in the area other thanthe memory cell area. Therefore, the surface flattening between thememory cell area and the other area can be easily performed withoutincreasing the number of steps.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1 is a schematic cross-sectional view showing DRAM accordingto an embodiment of a semiconductor storage device of the presentinvention;

[0029]FIG. 2 is a schematic cross-sectional view showing a manufacturingstep of DRAM of FIG. 1;

[0030]FIG. 3 is a schematic cross-sectional view showing anothermanufacturing step of DRAM of FIG. 1;

[0031]FIG. 4 is a schematic cross-sectional view showing anothermanufacturing step of DRAM of FIG. 1;

[0032]FIG. 5 is a schematic cross-sectional view showing anothermanufacturing step of DRAM of FIG. 1;

[0033]FIG. 6 is a schematic cross-sectional view showing anothermanufacturing step of DRAM of FIG. 1;

[0034]FIG. 7 is a schematic cross-sectional view showing anothermanufacturing step of DRAM of FIG. 1;

[0035]FIG. 8 is a schematic cross-sectional view showing anothermanufacturing step of DRAM of FIG. 1;

[0036]FIG. 9 is a schematic diagram of conventional DRAM;

[0037]FIG. 10 is a schematic cross-sectional view showing amanufacturing step of the conventional DRAM;

[0038]FIG. 11 is a schematic cross-sectional view showing anothermanufacturing step of the conventional DRAM;

[0039]FIG. 12 is a schematic cross-sectional view showing anothermanufacturing step of the conventional DRAM;

[0040]FIG. 13 is a schematic cross-sectional view showing anothermanufacturing step of the conventional DRAM;

[0041]FIG. 14 is a schematic cross-sectional view showing anothermanufacturing step of the conventional DRAM; and

[0042]FIG. 15 is a schematic cross-sectional view showing anothermanufacturing step of the conventional DRAM.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0043] Preferred embodiments according to the present invention will bedescribed hereunder with reference to the accompanying drawings.

[0044]FIG. 1 is a schematic cross-sectional view of DRAM according to anembodiment of a semiconductor storage device of the present invention.

[0045] In FIG. 1, reference symbol A represents a memory cell area, andreference symbol B represents a peripheral circuit area located so as tobe adjacent to the memory cell area A. Reference numeral 1 represents asemiconductor substrate, reference numeral 2 represents an elementseparation oxide film, reference numeral 3 represents a MOS transistorof one memory cell constituting the memory cell area A, and referencenumeral 4 represents a MOS transistor constituting the peripheralcircuit area B. Reference numeral 3 a represents the source/drain of theMOS transistor 3, and reference numeral 3 b represents the gate of theMOS transistor 3. Reference numeral 4 a represents the source/drain ofthe MOS transistor 4, and reference numeral represents the gate of theMOS transistor 4.

[0046] Reference numeral 5 represents a first insulating layer,reference numeral 6 represents a connection opening formed in theinsulating layer 5, and a conductive member 7 is filled in theconnection opening 6. The lower end portion of the conductive member 7is connected to one of the source/drain 3 a of the MOS transistor 3.

[0047] In the memory cell area A, the capacitor 8 constituting thememory cell is formed on the insulating layer 5. The capacitor 8 has apillar-shaped insulating member 8 a, a first capacitance electrode 8 bformed on the side surface of the pillar-shaped insulating member 8 a, acapacitance insulating film 8 c which is formed so as to cover thepillar-shaped insulating member 8 a and the first capacitance electrode8 b, and a second capacitance electrode 8d which is formed so as tocover the capacitance insulating film 8 c. The pillar-shaped insulatingmember 8 a is disposed so that a part of the lower end portion of thepillar-shaped insulating member 8 a is connected to the upper endportion of the conductive member 7, and the lower end portion of thefirst capacitance electrode 8 b is connected to the upper end portion ofthe conductive member 7.

[0048] In the peripheral circuit area B, a second insulating layer 9 isformed on the insulating layer 5. The second insulating layer 9 isformed at the same height as the pillar-shaped insulating member 8 a ofthe capacitor 8, and formed of the same insulating material as thepillar-shaped insulating member 8 a of the capacitor 8. The secondinsulating layer 9 serves as an interlayer insulating film.

[0049] As not shown, an insulating film or a wiring layer may be formedon the structure shown in FIG. 1.

[0050] The manufacturing process of the above DRAM will be describedwith reference to FIGS. 1 to 8.

[0051] First, as shown in FIG. 2, the element separation oxide film 2 isformed on the semiconductor substrate 1, and the MOS transistors 3, 4and the first insulating layer 5 are formed.

[0052] Subsequently, as shown in FIG. 3, the connection opening 6 isformed at the position corresponding to one of the source/drain 3 a ofthe MOS transistor 3 in the insulating layer 5, and the conductivemember 7 is filled in the connection opening 6 thus formed, whereby theconductive member 7 is connected to the source/drain 3 a.

[0053] Subsequently, as shown in FIG. 4, an insulating material layer 9′is formed on the insulating layer 5 in the memory cell area A and theperipheral circuit area B.

[0054] Subsequently, as shown in FIG. 5, a mask pattern is formed byphotolithography, and anisotropic etching is conducted to subject theinsulating material layer 9′ to a patterning treatment, thereby formingthe pillar-shaped insulting member 8 a such as cylindrical insulatingmember in the memory cell area A and the second insulating layer 9 inthe peripheral circuit area B. Accordingly, the pillar-shaped insulatingmember 8 a and the second insulating layer 9 are formed of the samematerial and the same height. A part of the upper portion of theconductive member 7 is covered by the pillar-shaped insulating member 8a, but the other part is exposed.

[0055] Subsequently, as shown in FIG. 6, a conductive film 8 b′ isdeposited on the overall surface of the intermediate product shown inFIG. 5 by a method such as CVD method or the like which is excellent instep coverage performance.

[0056] Subsequently, as shown in FIG. 7, by conducting the anisotropicetching, the conductive film is left only at the side surface of thepillar-shaped insulating member 8 a in the memory cell area A to formthe first capacitance electrode 8 b. At this time, the lower end portionof the first capacitance electrode 8 b is connected to the conductivemember 7.

[0057] Subsequently, as shown in FIG. 8, an insulating film 8 c′ isdeposited and formed on the overall surface of the intermediate productshown in FIG. 7 by the method such as CVD method which is excellent instep coverage performance, and a conductive film 8 d′ is deposited andformed on the insulating film 8 c′. Thereafter, the conductive film 8 d′and the insulating film 8 c′ are subjected to patterning, therebyobtaining the semiconductor storage device shown in FIG. 1.

[0058] As described above, according to this embodiment, thepillar-shaped insulating member 8 a and the second insulating layer 9are formed by the patterning of the insulating material layer 9′, andthus they are formed of the same insulating material and are formed atthe same height. Accordingly, without increasing the number of steps,there can be easily prevented occurrence of the difference in heightbetween the surfaces of the memory cell area A and the other area.

What is claimed is
 1. A semiconductor storage device having pluralmemory cells each containing a capacitor and a transistor, characterizedin that a first insulating layer is formed so as to cover saidtransistor, said capacitor is formed on said first insulating layer,said capacitor contains a pillar-shaped insulating member formed on saidfirst insulating layer, a first capacitance electrode formed on the sidesurface of said pillar-shaped insulating member, a capacitanceinsulating film formed on said first capacitance electrode and a secondcapacitance electrode formed on said capacitance insulating film, saidfirst insulating layer has a connection opening formed therein, and saidconnection opening is filled with a conductive member for connectingsaid first capacitance electrode and said transistor to each other. 2.The semiconductor storage device as claimed in claim 1, wherein a secondinsulating layer formed of the same insulating material as saidpillar-shaped insulating member of said capacitor is formed at the sameheight as said pillar-shaped insulating member of said capacitor on saidfirst insulating layer in at least a part of an area other than thememory cell area containing the plural memory cells.
 3. Thesemiconductor storage device as claimed in any one of claims 1 and 2,wherein said transistor is a MOS transistor, and the source or drain ofsaid MOS transistor is connected to said conductive member.
 4. A methodof manufacturing a semiconductor storage device having plural memorycells each containing a capacitor and a transistor, characterized bycomprising the steps of: forming the transistor on a semiconductorsubstrate; forming a first insulating layer so that the transistor iscovered by the first insulating layer; forming connection openings inthe first insulating layer at the positions corresponding to therespective memory cells; filling a conductive member in each of theconnection openings; forming an insulating material layer on the firstinsulating layer; subjecting the insulating material layer to apatterning treatment to form a pillar-shaped insulating member so that apart of the surface of the conductive member filled in each of theconnection openings is covered by the pillar-shaped insulating member;forming a first capacitance electrode on the side surface of thepillar-shaped insulating member; connecting the first capacitanceelectrode and the conductive member to each other, forming a capacitanceinsulating film on the first capacitance electrode; and forming a secondcapacitance electrode on the capacitance insulating film.
 5. Thesemiconductor storage device manufacturing method as claimed in claim 4,wherein the patterning treatment of the insulating material layer isperformed by using anisotropic etching.
 6. The semiconductor storagedevice manufacturing method as claimed in claim 4, wherein the formationof the first capacitance electrode is performed by forming a conductivematerial layer and patterning the conductive material layer withanisotropic etching.
 7. The above semiconductor storage devicemanufacturing method as claimed in claim 4, wherein the transistor is aMOS transistor, and each connection opening is formed at the positioncorresponding to the source or drain of the MOS transistor.
 8. Thesemiconductor storage device manufacturing method as claimed in any oneof claims 4 to 7, wherein the insulating material layer is also formedin an area other than the memory cell area containing the plural memorycells on the semiconductor substrate, and the insulating material layeris subjected to a patterning treatment so that a second insulating layerhaving the same height as the pillar-shaped insulating member of thecapacitor remains in the area other than the memory cell area.